1. Field of the Invention
The present invention relates to a transmitting and receiving apparatus which is to be mounted in a mobile unit such as an airplane, and particularly to a transmitting and receiving apparatus which digitally transmits a video and a sound.
2. Related Art of the Invention
Recently, a digital video/audio system according to the MPEG standard is practically used in satellite broadcasting, a CATV, etc. In a video/audio service in an airplane, an analog broadcasting system is mainly used at the present time. Such a system is desired to be replaced with a digital broadcasting system in which an image compression technique such as MPEG is combined with a digital modulation technique, so that the number of transmission channels is increased and services are individually provided to all seats (for example, Japanese Patent Publication (Kokai) No. HEI7-255043).
Hereinafter, an example of a transmitting and receiving apparatus of the prior art will be described with reference to the drawings.
FIG. 6 shows the configuration of a transmitting and receiving apparatus of the prior art. In FIG. 6, 61 denotes modulating means, 62 denotes first frequency converting means, 63 denotes amplifying/branching means, 64 denotes second frequency converting means, and 65 denotes demodulating means.
FIG. 7 shows the configuration of a PLL frequency synthesizer included in each of the first and second frequency converting means 62 and 64. In FIG. 7, 71 denotes a PLL synthesizer IC, 72 denotes a loop filter, 73 denotes a voltage controlled oscillator, and 74 denotes a crystal oscillator.
The operation of the thus configured transmitting and receiving apparatus will be described.
First, video data and audio data which have been converted into a digitized form are input to the modulating means 61. The modulating means 61 performs quadrature amplitude modulation (hereinafter, abbreviated as QAM modulation) which is used in a CATV and the like, or vestigial sideband modulation (hereinafter, abbreviated as VSB modulation) on the data and produces a signal of a center frequency f1.
As the center frequency f1, frequently, 44 or 43.75 MHz is used in Japan and USA, and 36.125 MHz is used in Europe. A signal output from the modulating means 61 is input to the first frequency converting means 62.
In the first frequency converting means 62, the center frequency of the input signal is converted from f1 to f2. In an airplane, a frequency in a frequency band of several tens to several hundreds MHz is usually used as the center frequency f2. A signal output from the first frequency converting means 62 is input to the amplifying/branching means 63.
The amplifying/branching means 63 amplifies and branches the input signal, and outputs the amplified and branched signals in order to distribute the signals to various areas of the airplane. The signals output from the amplifying/branching means 63 are input to the second frequency converting means 64. In the second frequency converting means 64, the center frequency of each of the input signals is converted from f2 to f3.
The center frequency f3 is equal to the frequency f1. The signals output from the second frequency converting means 64 are input to the demodulating means 65. The demodulating means 65 demodulates the input signals and outputs reproduced data.
In each of the first and second frequency converting means 62 and 64, a PLL frequency synthesizer is used. Hereinafter, the operation of a PLL frequency synthesizer will be described with reference to FIG. 7.
The crystal oscillator 74 is connected to the PLL synthesizer IC 71, and generates a signal Sxtal by using an internal oscillation circuit. The signal Sxtal is converted into a signal Sref by an internal programmable frequency divider (hereinafter, referred to as R counter).
When the frequency of the crystal oscillator 74 is set to 4 MHz and the R counter is set to 16, for example, the signal Sref has a frequency of 4 MHz/16=250 kHz. On the other hand, a signal Svco is input to the PLL synthesizer IC 71 from the voltage controlled oscillator 73. The signal Svco is converted by another internal programmable frequency divider (hereinafter, referred to as MA counter) into a signal Sdiv. When the MA counter is set to 2,800, for example, the relationship of the signal Sdiv=Svco/2,800 is established.
A phase comparator included in the PLL synthesizer IC 71 compares the phases of the signals Sref and Sdiv with each other, and produces a signal Serr which is proportional to the phase difference. For example, when the phase of the signal Sdiv leads that of the signal Sref, the signal Serr of a positive voltage is output. By contrast, when the phase of the signal Sdiv lags that of the signal Sref, the signal Serr of a negative voltage is output, and, when the phase of the signal Sdiv coincides with that of the signal Sref, the signal Serr of a zero voltage is output.
The signal Serr output from the PLL synthesizer IC 71 is input to the loop filter 72. The loop filter 72 has a frequency characteristic of allowing only a signal of a low frequency region to pass therethrough, and smoothes the input signal to remove noise components. A signal output from the loop filter 72 is input to the voltage controlled oscillator 73.
The voltage controlled oscillator 73 is an oscillator in which the oscillation frequency is changed in accordance with the level of the input signal. As the voltage level of the input signal is higher, for example, the frequency of an output signal is higher.
When the PLL frequency synthesizer is configured as described above, the phase of the signal Sdiv is controlled so as to coincide with that of the signal Sref. Therefore, the signal Svco output from the voltage controlled oscillator 73 has a frequency of Sref×2,800=250 kHz×2,800=700 MHz. When the setting of the MA counter is changed, a different oscillation frequency can be obtained from the voltage controlled oscillator 73 (for example, “PLL SHUHASU SYNTHESIZER KAIRO SEKKEI HO,” 1994, SOGO DENSHI SHUPPANSHA).
As a result, when PLL frequency synthesizers are used as the oscillators respectively included in the first and second frequency converting means 62 and 64, the frequency f2 can be changed in the range of several tens to several hundreds MHz.
Large mechanical shocks and vibrations are applied to the transmitting and receiving apparatus which is mounted in an airplane. Such mechanical shocks and vibrations increase errors in the reproduced data output from the demodulating means 65. The data error is caused mainly by noises which are generated by externally applied mechanical shocks and vibrations from a capacitor of the loop filter 72, and a capacitor and a coil of the voltage controlled oscillator 73 in the first and second frequency converting means 62 and 64. Therefore, the phase noise characteristics of the signals output from the PLL frequency synthesizers are impaired.
As a method of suppressing noises which are generated by mechanical shocks and vibrations from a PLL frequency synthesizer, the following methods have been proposed.
As a first proposal, a method is proposed in which a PLL frequency synthesizer is mounted on a mini module circuit board and the module circuit board is implanted into the main circuit board (Japanese Patent Publication (Kokai) No. HEI6-85700). In the method, when vibrations are applied, the vibrations are first absorbed by the main circuit board to suppress transmission of the vibrations to the mini module circuit board on which the PLL frequency synthesizer is mounted, and no consideration is given to devices used in the PLL frequency synthesizer and the circuit constants of the PLL.
As a second proposal, a method is proposed in which a capacitor used in a loop filter of a PLL frequency synthesizer is configured by a non-laminated capacitor (Japanese Patent Publication (Kokai) No. HEI7-288483). In the method, the piezoelectric effect is reduced by the user of a non-laminated capacitor, and no consideration is given to the circuit constants of the PLL.
As a third proposal, a method is proposed in which capacitors used in a loop filter of a PLL frequency synthesizer are mounted on the front and back faces of a circuit board, and electrically connected in parallel to each other (Japanese Patent Publication (Kokai) No. HEI9-219576). In the method, the mounting of capacitors on the front and back faces of a circuit board enables the capacitors to be compensated with each other even when the circuit board is bent, and no consideration is given to devices used in the PLL frequency synthesizer and the circuit constants of the PLL.
Furthermore, the first to third proposals are methods of suppressing noises which are generated by mechanical shocks and vibrations from a PLL frequency synthesizer, and fail to consider portions of a transmitting and receiving apparatus other than the PLL frequency synthesizer.
In a transmitting and receiving apparatus which transmits digitized video and audio data, the above-mentioned countermeasures that, as described above, are performed on a loop filter or a PLL frequency synthesizer or a circuit board on which a PLL frequency synthesizer is mounted are insufficient for attaining a desired effect under an environment of severe shocks and vibrations in an airplane. Therefore, such an apparatus remains to have a problem in that data errors cannot be suppressed.